The present invention relates to manufacturing methods of semiconductor devices, and more specifically, to a technique that can be suitably applied to a manufacturing method of a semiconductor device including a metal-insulator-semiconductor field-effect transistor (MISFET).
A MISFET can be formed by depositing a gate insulating film over a semiconductor substrate, forming a gate electrode over the gate insulating film, forming low-concentration regions for source and drain by ion implantation, and forming high-concentration regions for the source and drain by ion implantation after forming sidewall spacers on sidewalls of the gate electrode.
Japanese Unexamined Patent Publication No. Hei 06 (1994)-181293 (Patent Document 1) discloses a technique for making an offset length of a source/drain of a transistor for high voltage longer than that of a source/drain of a normal transistor by increasing the width of a sidewall insulating film of the high-voltage transistor as compared to that of a sidewall insulating film of the normal transistor.
Japanese Unexamined Patent Publication No. 2006-203225 (Patent Document 2) discloses a technique for forming a metal silicide layer in a high-concentration region self-aligned with a gate sidewall layer in a MISFET for the high-speed operation, and also for forming another metal silicide layer in another high-concentration region in contact with a LDD portion having a larger width than that of the gate sidewall layer in another MISFET for the high-voltage drive.
Japanese Unexamined Patent Publication No. 2001-93984 (Patent Document 3) discloses a technique for forming a sidewall 123 and another thicker sidewall 113.